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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">ID_ISAR5, Instruction Set Attribute Register 5</h1><p>The ID_ISAR5 characteristics are:</p><h2>Purpose</h2>
        <p>Provides information about the instruction sets implemented by the PE in AArch32 state.</p>

      
        <p>Must be interpreted with <a href="AArch32-id_isar0.html">ID_ISAR0</a>, <a href="AArch32-id_isar1.html">ID_ISAR1</a>, <a href="AArch32-id_isar2.html">ID_ISAR2</a>, <a href="AArch32-id_isar3.html">ID_ISAR3</a>, and <a href="AArch32-id_isar4.html">ID_ISAR4</a>.</p>

      
        <p>For general information about the interpretation of the ID registers see <span class="xref">'Principles of the ID scheme for fields in ID registers'</span>.</p>
      <h2>Configuration</h2><p>AArch32 System register ID_ISAR5 bits [31:0] are architecturally mapped to AArch64 System register <a href="AArch64-id_isar5_el1.html">ID_ISAR5_EL1[31:0]</a>.</p><p>This register is present only when EL1 is capable of using AArch32. Otherwise, direct accesses to ID_ISAR5 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>ID_ISAR5 is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="4"><a href="#fieldset_0-31_28">VCMA</a></td><td class="lr" colspan="4"><a href="#fieldset_0-27_24">RDM</a></td><td class="lr" colspan="4"><a href="#fieldset_0-23_20">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-19_16">CRC32</a></td><td class="lr" colspan="4"><a href="#fieldset_0-15_12">SHA2</a></td><td class="lr" colspan="4"><a href="#fieldset_0-11_8">SHA1</a></td><td class="lr" colspan="4"><a href="#fieldset_0-7_4">AES</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">SEVL</a></td></tr></tbody></table><h4 id="fieldset_0-31_28">VCMA, bits [31:28]</h4><div class="field">
      <p>Indicates AArch32 support for complex number addition and multiplication where numbers are stored in vectors. Defined values are:</p>
    <table class="valuetable"><tr><th>VCMA</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>The VCMLA and VCADD instructions are not implemented in AArch32.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>The VCMLA and VCADD instructions are implemented in AArch32.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_FCMA</span> implements the functionality identified by <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.3, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-27_24">RDM, bits [27:24]</h4><div class="field">
      <p>Indicates support for the VQRDMLAH and VQRDMLSH instructions in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>RDM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>No VQRDMLAH and VQRDMLSH instructions implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>VQRDMLAH and VQRDMLSH instructions implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_RDM</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.1, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-23_20">Bits [23:20]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-19_16">CRC32, bits [19:16]</h4><div class="field">
      <p>Indicates support for the CRC32 instructions in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>CRC32</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>CRC32 instructions are not implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>CRC32B, CRC32H, CRC32W, CRC32CB, CRC32CH, and CRC32CW instructions are implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p><span class="xref">FEAT_CRC32</span> implements the functionality identified by the value <span class="binarynumber">0b0001</span>.</p>
<p>In Armv8.0, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p>
<p>From Armv8.1, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-15_12">SHA2, bits [15:12]</h4><div class="field">
      <p>Indicates support for the SHA2 instructions in AArch32 state.</p>
    <table class="valuetable"><tr><th>SHA2</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>No SHA2 instructions implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-11_8">SHA1, bits [11:8]</h4><div class="field">
      <p>Indicates support for the SHA1 instructions are implemented in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>SHA1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>No SHA1 instructions implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 implemented.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0001</span>.</p></div><h4 id="fieldset_0-7_4">AES, bits [7:4]</h4><div class="field">
      <p>Indicates support for the AES instructions in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>AES</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>No AES instructions implemented.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>AESE, AESD, AESMC, and AESIMC implemented.</p>
        </td></tr><tr><td class="bitfield">0b0010</td><td>
          <p>As for <span class="binarynumber">0b0001</span>, plus VMULL (polynomial) instructions operating on 64-bit data quantities.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the permitted values are <span class="binarynumber">0b0000</span> and <span class="binarynumber">0b0010</span>.</p></div><h4 id="fieldset_0-3_0">SEVL, bits [3:0]</h4><div class="field">
      <p>Indicates support for the SEVL instruction in AArch32 state. Defined values are:</p>
    <table class="valuetable"><tr><th>SEVL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0000</td><td>
          <p>SEVL is implemented as a NOP.</p>
        </td></tr><tr><td class="bitfield">0b0001</td><td>
          <p>SEVL is implemented as Send Event Local.</p>
        </td></tr></table><p>All other values are reserved.</p>
<p>In Armv8-A, the only permitted value is <span class="binarynumber">0b0001</span>.</p></div><div class="access_mechanisms"><h2>Accessing ID_ISAR5</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRC{&lt;c&gt;}{&lt;q&gt;} &lt;coproc&gt;, {#}&lt;opc1&gt;, &lt;Rt&gt;, &lt;CRn&gt;, &lt;CRm&gt;{, {#}&lt;opc2&gt;}</h4><table class="access_instructions"><tr><th>coproc</th><th>opc1</th><th>CRn</th><th>CRm</th><th>opc2</th></tr><tr><td>0b1111</td><td>0b000</td><td>0b0000</td><td>0b0010</td><td>0b101</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HSTR_EL2.T0 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HSTR.T0 == '1' then
        AArch32.TakeHypTrapException(0x03);
    elsif EL2Enabled() &amp;&amp; !ELUsingAArch32(EL2) &amp;&amp; HCR_EL2.TID3 == '1' then
        AArch64.AArch32SystemAccessTrap(EL2, 0x03);
    elsif EL2Enabled() &amp;&amp; ELUsingAArch32(EL2) &amp;&amp; HCR.TID3 == '1' then
        AArch32.TakeHypTrapException(0x03);
    else
        R[t] = ID_ISAR5;
elsif PSTATE.EL == EL2 then
    R[t] = ID_ISAR5;
elsif PSTATE.EL == EL3 then
    R[t] = ID_ISAR5;
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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